library verilog;
use verilog.vl_types.all;
entity Control is
    port(
        oPCode          : in     vl_logic_vector(5 downto 0);
        regDst          : out    vl_logic;
        branch          : out    vl_logic;
        memRead         : out    vl_logic;
        mem2reg         : out    vl_logic;
        memWrite        : out    vl_logic;
        ALUsrc          : out    vl_logic;
        regWrite        : out    vl_logic;
        ALUop           : out    vl_logic_vector(2 downto 0)
    );
end Control;
